Semiconductor silicon carbide (SiC) has considerable bandgap energy in comparison with silicon that is widely used in devices, and is suitable for high voltage, high power, and high temperature operation. There are high expectations for its application to power devices and other components. The structure of SiC power devices, for which research and development are being actively carried out, can mainly be divided into two classes: MOS devices and Junction devices. The present invention relates to a performance improvement in static induction transistors (SIT), junction field effect transistors (JFET), and other junction transistors.
Following are reported examples of SITs and JFETs in which SiC has been used.
Examples of a typical SIT have been disclosed in 600V5A 4H—SiC SIT with Low RonS of 13 mΩcm2 (Takashi Shinohe, and others, Proceedings of the Symposium on Static Induction Devices, Vol. 17, pp. 41-45) and 2002 Report on the Results of Research Sponsored by New Energy and Industrial Technology Development Organization, Development of Ultra Low Loss Power Devices Technology, and Device Design Technology (Research and Development Association for Future Electron Devices). FIG. 11 shows a cross-sectional schematic view of the SIT disclosed in 600V5A 4H—SiC SIT with Low RonS of 13 mΩcm2 by Takashi Shinohe, and others (Proceedings of the Symposium on Static Induction Devices, Vol. 17, pp. 41-45). The SIT 100 has a drain region 101 (an n-type low-resistance layer), a drift region 102 (an n-type high-resistance layer), source regions 103 of an n-type low-resistance region, gate regions 104 of a p-type low-resistance region formed so as to surround the source regions, a drain electrode 105, source electrodes 106, and gate electrodes 107. Channel regions 108 are formed between the gate regions 104. The SIT 100 does not have a channel-doped layer inside the drift region 102, and is a static induction transistor that exhibits a normally-on characteristic, which is in a conducting state when voltage is not applied to the gate electrodes 107. This is dependent on an PET (Field Effect Transistor) operation in which positive holes (which are minority carriers) are not injected into the channel region 108 from the gate region 104. It is for this reason that special contrivances are not required to inhibit recombination of electrons and positive holes in the surface between the gate and source.
An example of a JFET is disclosed in 6A, 1 kV 4H—SiC Normally-off Trenched-and-Implanted Vertical JFETs (J. H. Zhao, et al., Materials Science Forum Vols. 457-460 (2004), pp. 1213-1216). FIG. 12 shows a cross-sectional structural view of a JFET disclosed in the preceding reference. The JFET 110 has a drain region 111 (an n-type low-resistance layer), a drift region 112 (an n-type high-resistance layer), source regions 113 of an n-type low-resistance layer, a p-type low-resistance region, p-type low-resistance gate regions 114, passivation films 115, a drain electrode 116, source electrodes 117, gate electrodes 118, trench portions 119, and a source metal layer 120. The width d of the source of the JFET is very narrow in a range of 1.45 μm to 1.95 μm The depth D of the channel region is considerable at 2.1 μm Therefore, with this JFET, in order to set the normally-off characteristic (non-conductive state) when voltage is not applied to the gate electrode 118, the width of the source must be made less than 1.95 μm, and such a width is very difficult to produce. In order to reduce the resistance of the gate region 114, a material with a high concentration of impurities is selected.
FIGS. 13A, 13B, and 13C are views that describe the operation of a typical junction transistor. In FIGS. 13A, 13B, and 13C, reference numeral 200 is a drain electrode, 201 is a drain region, 202 is a drift region, 203 is a source region, 204 is a gate region, 205 is a source electrode, 206 is a gate electrode, and 207 is a surface protective layer. In this junction transistor, a voltage is applied to the drain electrode 200, the source electrode 205 disposed on both surfaces of the substrate, and the main electric current that flows between the source and drain is controlled by signals applied to the gate electrode 206 disposed so as to surround the source region 203.
In this junction transistor, main electric current does not flow in a state in which an OFF signal is applied to the gate electrode 206. In the normally-on device described above, a negative voltage acting as an off signal must be applied to the gate electrode in order to switch the device off. When an OFF signal is presented to the gate region 204, a depletion region dr expands inside the drift region 202, and electrons (arrow e) can no longer travel from the source region 203 through the drift region 202, as shown in FIG. 13A. A negative voltage is applied in a normally-on transistor in order to achieve such a state (pinch off). Also, this state is ordinarily achieved at 0 V in a normally-off transistor. FIG. 13B shows the state in which a higher voltage than the voltage in the pinch-off state is applied to the gate electrode 206. When a voltage that is higher than the voltage in the pinch-off state is applied as the gate voltage, the depletion region dr is reduced, the transistor is set in an ON state, and an electron current (arrow e) flows from the source electrode 205 to the drain electrode 200. When the voltage applied to the gate electrode 206 is increased, positive holes are injected (arrow h) from the gate region 204 to the drift region 202, as shown in FIG. 13C. Electrons are injected from the source region 203 due to the positive hole injection, and the electrical conductivity of the drift region increases so that the positive electric charge created by the injection of positive holes in the n-type drift region is neutralized. The ON resistance is thereby further reduced.
Thus, it is effective to apply the positive voltage to the gate electrode and increase the electrons injected from the source region into the drift region in order to obtain a lower ON voltage (resistance). In this case, the pn junction formed between the gate and source is given a forward bias, and the positive-hole electric current flows from the gate electrode to the source electrode. In order to operate the SIT at high efficiency, more drain electric current is preferably controlled with less gate electric current. For this reason, the electric current amplification factor (=drain electric current/gate electric current) is an important parameter.
Considered next is the effect of the surface states between the gate and source on the characteristics. A large number of surface states caused by uncombined atoms is present in the surface of the semiconductor. Subjecting silicon to thermal oxidation makes it possible to create a silicon oxide film boundary with few interface states that do not adversely affect the device characteristics. With SiC, on the other hand, it is currently impossible to sufficiently reduce the interface states by using thermal oxidation, and heat treatment (POA: Post Oxidation Annealing) and other processes performed thereafter. For this reason, when a forward bias is applied to the gate electrode 206 to cause a junction transistor such as that shown in FIG. 13C to operate, the positive holes (arrow h2) injected from the gate region 204 and the electrons (arrow e2) injected from the source region 203 recombine via the recombination states (indicated by the symbol “x” in the drawing) of the surface of the SiC surface between the gate and source, and the electric current amplification factor is reduced.
Described next is the normally-off characteristic. When some abnormality occurs and the control signal to the gate electrode is cut off in a power device, the device is preferably set in an OFF state. For this reason, it is an important condition that power devices have a normally-off characteristic. In order for the structure of FIG. 11 described above to have a normally-off characteristic, the distance between adjacent gates and the width of the source must be made very narrow. FIGS. 14A and 14B illustrate a comparison of a conventional device having a narrow source and a device having a wide source. FIG. 14A shows the case in which the source is narrow and FIG. 14B shows the case in which the source is wide. Reference numeral 200 is a drain electrode, 201 is a drain region, 202 is a drift region, 203 is a source region, 204 is a gate region, 205 is a source electrode, 206 is a gate electrode, and 207 is a surface protective film.
When the source is made narrow and the distance between the gates is reduced as in the device shown in FIG. 14A, manufacturing becomes difficult; the effective region (shown by reference symbol ER in the figure) of the entire device surface area is reduced, as shown in the view; and the ON voltage (resistance) increases as a result.
In the case of the SIT shown in FIG. 11, since a means is not provided for inhibiting the recombination of electrons and positive holes in the SiC surface between the source and gate, a considerable amount of recombination occurs in the SiC surface when a minority carrier is injected from the gate electrode, and the characteristics do not improve in a bipolar mode operation in which conductivity is modulated in the high-resistance layer between the drain and the source. Also, since channel doping is not adopted in the structure, it is very difficult to obtain a normally-off characteristic.
In order to obtain a normally-off characteristic in the case of the JFET shown in FIG. 12, a very small trench structure having a width of 1.5 μm and a depth of about 2 μm must be made, and a gate layer must also be provided to the side walls of the trench, resulting in difficult manufacture. Also, the percentage of the source region that occupies the device must be made smaller, which hinders improvement of the ON voltage (resistance).
There is a drawback in that when a forward bias is applied to the gate electrode to operate a conventional junction transistor, the positive holes injected from the gate region and the electrons injected from the source region recombine via the surface states of the SiC surface between the gate and source, and the electric current amplification factor is reduced.
In order to obtain a normally-off characteristic in a conventional junction transistor, the distance between adjacent gates and the width of the source must be made very narrow. When the width of the source is narrowed and the distance between gates is reduced, there is a drawback in that manufacturing becomes difficult, the effective region of the entire device surface area is reduced, and the ON voltage (resistance) increases as a result.
There is therefore a need to provide a junction semiconductor device and to establish a method for manufacturing a junction semiconductor device whose structure makes it possible to establish simple steps for manufacturing a high-performance junction device having a normally-off characteristic that is required in the motor control of automobiles and other applications.